The present invention relates to a semiconductor device and method of manufacturing the semiconductor device and, more particularly, technique reducing contact resistance at contacting upper layer and lower layer. Further the invention relates to forming a bump electrode.
Explanation is made below on the conventional semiconductor device and method of manufacturing the semiconductor device, with reference to the drawings.
In FIG. 14, numeral 1 denotes a semiconductor substrate, on which a gate electrode 3 is formed through gate oxide film 2, and source/drain regions 4 are formed so as to be adjacent to the gate electrode 3. A interlayer insulating film 5 covering the gate electrode 3 is formed, and source/drain electrodes 7 contacting the source/drain regions 4 through contact holes 6 formed at the interlayer insulating film 5 are formed.
In FIG. 15 and FIG. 16, numeral 11 denotes a semiconductor substrate, on which an insulating film 12 including LOCOS oxide film is formed, and a lower layer wiring 13 is formed on the insulating film 12.
An interlayer insulating film 14 is formed so as to cover the lower layer wiring 13, and an upper layer wiring 16 is formed so as to contact the lower wiring 13 through via holes 15 formed at the interlayer insulating film 14.
A passivation film 17 is formed so as to cover the upper layer wiring 16, and a gold bump electrode 18 is formed at a pad portion 17A where the passivation film 17 is opened.
Here, in the semiconductor device shown in FIG. 14, step coverage of metal film in a contact hole decreases in accordance with the reduction of the contact hole when metal film such as Al and the like is deposited by spattering method at forming the source/drain electrode. Because of that, a device is made practicable nowadays, wherein film such as tungsten film and the like having conductivity in the contact hole is buried by CVD method and, on the film, metal film such as Al etc. is formed for metal wiring layer by patterning.
In the case of constitution of various kinds of transistors adopting such the plug contact technique, when sizes of contact holes are various, recess depth at etch back after burying become various, and to say extremely, the recess values possibly become worse to similar degree as the case without burring step coverage of metal film.
Because of that, in the case of constitution of various kinds of transistors by michronization process such as 0.35 μm, it is need to make each size of contact hole even to the size of contact hole of the transistor in the minimum design rule, and contact resistance becomes high in some transistor so that there is a problem of rise of on-resistance.
In the semiconductor device shown in FIG. 15 and FIG. 16, when there are the via holes 15 under the above-mentioned pad portion, difference in surface of the via holes remains even on surface of the gold bump electrode 18. Because of that, difference in surface of the gold bump electrode 18 causes decrease of yield at mounting on mounting points of TAB (Tape Automated Bonding) and the like for example.
Especially, in the case of constitution of various kinds of transistors by michronization process such as 0.35 μm, opening diameter of the pad portion is constituted by plural micro via holes because the minimum dimension is applied for dimension of each via hole (contact hole). Because of that, difference in surface remains like surface of the above-mentioned gold bump electrode 18.